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features ? antenna driver stage with adjustable antenna peak current for up to 1.5a frequency tuning range from 100 khz to 150 khz automatic antenna peak current regulation self-tuning oscillator for antenna resonant frequency adaptation capable of driving a high-q antenna integrated 5v regulator for external load up to 10 ma bi-directional single wire inte rface for microcontroller or ecu lf baud rates up to 4 kbaud and amplitude shift keying (ask) modulation low power standby mode < 50 a antenna driver diagnosis: peak current, antenna frequency and battery voltage monitoring power supply range 8v to 24v direct battery input load dump protection operation at temperature ?40c to +105c emi and esd according to automotive requirements highly integrated, fewer ex ternal compon ents required overtemperature protection applications tire pressure measurement (tpm) benefits self tuning capability to antenna resonance frequency adjustable antenna peak current value highest integration level for embedded automotive systems 1. description the ata5276 is an integrated 1.5a peak current bcdmos antenna driver ic dedi- cated as a 125 khz wake-up channel transmitter for tpm applications. it includes the full functionality to generat e a magnetic lf field in conjunction with an antenna coil to transmit data and power to a receiver. the transmission can be con- trolled via a one wire i/o-interface by an external unit. the smart power ic is delivered in a qfn20 power package with heat slug. 125 khz transmitter ic for tpm ata5276 preliminary 4909b?auto?04/06
2 4909b?auto?04/06 ata5276 [preliminary] 2. general description the ata5276 is a 125-khz transmitter ic. it is dedicated to driving 125 khz lc antenna tanks, specifically for the wake-up channel in tire pressure measurement (tpm) applications. it includes a control logic with vco which generates the 125 khz signal for the output driver stage. a phase lock circuit regulates the driv er output frequency on the antenna resonance fre- quency, achieving a maximum field strength on the antenna. the driver duty cycle is regulated and stabilizes the ante nna current for a wide supply voltage range. the ic can be controlled by a microcontroller or ecu via the one wire bi-directional interface. it is used for the data transmissi on and to indicate errors. for the data transmis sion ask modula- tion is used. the antenna signal is modulated by the dio interface line. the ic has a build in diagnosis function and detects detuning and broken or short wire of the antenna circuitry. if a failure is detected the ic indicates it by an error signal via the dio line. the integrated 5v regulator can be used externally for a load up to 10 ma. figure 2-1. block diagram ata5276 125-khz transmitter 5v reg k- line ref gate drive control state machine 19 boost 14 tm2 15 tm1 13 tm3 9 sense 6 dvss3 8 dvss1 7 dvss2 3 drv3 4 drv2 2 dvcc1 1 dvcc2 10 vss 5 drv1 half bridge 12 rcr 11 rext 17 dio 16 vdio 18 vcc 20 dvcc3 bias vco xor
3 4909b?auto?04/06 ata5276 [preliminary] 3. pin configuration figure 3-1. pinning qfn20 ata5276 19 boost 14 tm2 15 tm1 13 tm3 9 sense 6 dvss3 8 dvss1 7 dvss2 3 drv3 4 drv2 2 dvcc1 1 dvcc2 10 vss 5 drv1 12 rcr 11 rext 17 dio 16 vdio 18 vcc 20 dvcc3 table 3-1. pin description pin (1) symbol function 1 dvcc2 battery supply input 2 dvcc1 battery supply input 3 drv3 antenna driver stage output 4 drv2 antenna driver stage output 5 drv1 antenna driver stage output 6 dvss3 power supply ground 7 dvss2 power supply ground 8 dvss1 power supply ground 9 sense current zero crossing sense input 10 vss analog and digital ground 11 rext external reference current input 12 rcr external reference for antenna peak current 13 tm3 for test purposes only 14 tm2 for test purposes only 15 tm1 for test purposes only 16 vdio dio line interface voltage selection 17 dio one-wire serial interface line 18 vcc 5v supply output (for external storage capacitor only) 19 boost external bootstrap cap 20 dvcc3 battery supply input note: 1. pin numbers valid for all revisions of the ata5276
4 4909b?auto?04/06 ata5276 [preliminary] 4. functional description 4.1 operation modes there are two different operation modes for the ata5276: standby mode transmission mode 4.2 standby mode and wake-up after power-on-reset, the ata5276 is in standby mode. for minimum power consumption, only the internal 5v supply and the dio line interface are active. the ic can be activated by the exter- nal control unit via the serial interface. the dio line is called logic high if it is pulled up to the vdio voltage level. the di o line is called logic low if it is pu lled down to the vss voltage level. a low signal at the dio line wakes-up the ic. the circuit enters the standby mode if eith er of these three co nditions are fulfilled: 1. after power-on-reset and the dio is high (see figure 4-1 ) 2. after a time out of t outl (1) during which dio is permanently low (see figure 4-3 on page 5 ) 3. after a time out of t outh (2) during which dio is permanently high and an acknowledge time t ack /t err (1) (see figure 4-2 ) notes: 1. time does not depend on the antenna resonance frequency. 2. time depends on the antenna resonance frequency. figure 4-1. stby after por figure 4-2. stby after dio = h t t stby dio por t t t stby tout_h tack/terr dio
5 4909b?auto?04/06 ata5276 [preliminary] figure 4-3. stby after dio = l 4.3 transmission mode 4.3.1 ask modulation for the transmission of a wake-up signal or data to a receiver, the ata5276 generates a antenna resonance synchronized signal at the antenna driver output (drv pin). a connected lc antenna radiates a magnetic field. for the da ta transmission the field can be 100% amplitude modulated by the dio interface input. if a low level signal is applied at the dio pin, the driver generates a square wave signal drv for the antenna. if a high level signal is applied at the dio pin the driver is stopped and switched to ground. in this way ask modulat ed data can be trans- mitted (see figure 4-4 ). figure 4-4. data transmission 4.3.2 anti-bouncing filter in transmission mode the dio input signal is delayed for a anti-bouncing time. the driver is switched on after a delay time of t dl (typically 64 s) if the dio is pulled to a low level continuously. the driver is switched-off after a delay time of t dh if the dio is pulled to high level. the t dh time depends on the antenna resonance frequency, suppressing short disturbance pulses from the dio line. figure 4-5. anti-bouncing t t stby tout_l dio dio drv coil td_l td_h
6 4909b?auto?04/06 ata5276 [preliminary] 4.3.3 time out and time out reset the ic has a time out supervisor for the interfac e line to avoid unintended continuous transmis- sion in case of line errors. the time out timer runs if the dio pin is pulled to a low level. if the dio pin is permanently low for more than the time t outl the driver is switched off and the ic enters the standby mode. this avoids the discharging of the supply battery if the dio line has a failure like a body contact or another permanent low level failure. the time t outl depends on the antenna resonance frequency. figure 4-6. time out and time out reset protocol for continuous transmission periods the internal ti me out timer must be reset within the time out reset period t orp with a short high pulse of length t or at dio. any transmission time periods can be made by cyclical resetting of the time out timer (see figure 4-6 ). the time t orp and t or depends on the antenna resonance frequency. 4.3.4 transmission acknowledge and error signal if no failure is detected during a transmission sequence the ic acknowledges the transmission by pulling the dio line to low level for time t ack (typically 256 s). the acknowledge signal is generated at the end of a transmission sequence if the dio line was high for the time t outh (typ- ically 16 ms). their are two types of error detection (see section ?diagnosis and protection? on page 8 ): immediate switch-off of the driver stage the failure is indicated through the dio line based on transmission acknowledge and error signal at the end of transmission the ic indicates the failure by an erro r signal by pulling the dio line to a low level for time t err (typically 128 s) instead of t ack . with the acknowledge and the error signal a conn ected microcontroller is able to recognize fail- ures of the ic or the antenna module as well as dio line failures like a broken wire or a short circuit. dio drv standby transmission delay time out td_l tout_l standby tor timeout reset torp time out reset periode td_h transmission delay
7 4909b?auto?04/06 ata5276 [preliminary] figure 4-7. transmission acknowledge and error signal the various failure types are monitored during transmission in time tfdx (see section ?diagno- sis and protection? on page 8 ). the time tfdx depends on the antenna resonance frequency. 4.4 internal voltage regulator and por the ic contains a 5-v regulator. it is used for the supply voltage v cc of the logic circuits and the low voltage analog circuits. additionally, the v cc can be used externally for loads up to 10 ma. the stabilized voltage is available at pin vcc and must be buffered with an exte rnal capacitor. 4.4.1 reset after power on or after a voltage breakdown the power-on-reset circuit of the ic generates a reset pulse which sets the logic circuit to a defined initial state. a reset is generated if the vcc is below the reset threshold voltage v por and after power on. 4.4.2 dio interface the interface can be operated either as a 5-v microcontroller interface or as automotive k-line interface with the car battery voltage. in which mode it operates must be selected with the vdio pin. if it is connected to 5v the dio pin operates as microcontroller interface and if it is con- nected with the battery voltage it operates as automotive interface according to the k-line specification. 4.5 oscillator and carrier frequency generation a voltage controlled oscillator (vco) is used to clock the interface logic and the gate driver logic. the antenna driver output signal drv is derived from this clock. the vco operates in two modes: the self-oscillation mode with clock clk so and the resonance tracking mode with clock clk rt . 4.5.1 self-oscillating mode if the antenna half-br idge is not activate d the vco is in self-oscillating mode. it runs at a center frequency clk so of typically 125 khz with an accuracy of 8%. for that purpose, an external reference resistor has to be applied to pin rext. the resistor at pin rext determines the vco frequency proportionally. the recommended value is 100 k ? achieving 125 khz oscillator frequency. dio drv coil time out acknowledge tack tout_h failure detection tdfx time out tout_h error signal terr failure
8 4909b?auto?04/06 ata5276 [preliminary] 4.5.2 resonance tracking mode in case the antenna half-bridge is activated the vco is tracked by the antenna current by means of it zero crossing detection. the vco runs at the antenna resonance frequency stationary. the clock clk rt deviates 1.4% from the antenna resonance frequency, depending on the antenna quality and resonance frequency (see section ?application hints? on page 14 ). for that purpose, an antenna current shunt resistor has to be applied to the sense pin. the shunt resistance is used internally for the zero crossing detection of the antenna current only. by this feature the antenna operates with the maximum voltage, current and field strength. it is recommended specially for systems with high ant enna q-factors and low lc tolerances. 4.6 coil driver output and an tenna peak current control the driver circuit consists on a dmos half-b ridge designed for 1.5a peak current with low on-resistance rdson. it is short-circuit and overtemperature protected (see section ?diagnosis and protection? on page 8 ). the half-bridge is switched on by a low level signal at dio and gen- erates a square wave voltage for the antenna rlc circuitry. a very useful function of the driver stage is the build-in antenna current control loop. the ic senses the current through the antenna internally and controls the peak value ia peak by control- ling the duty cycle dc drv of the driver output. so the antenna can be designed for maximum antenn a current with the typical or even the mini- mum supply voltage. for higher supply voltages t he current is controlled by reducing the driver duty cycle. the reference value for the antenna current ia peak can be adjusted externally with a resistor r cr at the rcr pin. note: applying the formula above, the right driver current for the antenna has to be adjusted for the worst supply voltage case. the ic operates from 14% up to 86% duty cycle for that case and reduces the duty cycle for higher voltages (for the definition of the duty cycle dc drv , see ?applica- tion hints? on page 14 ). this feature allows the user to operate the ic in a wide field of operational voltage field and pro- tects the driver stage and the antenna from antenna overcurrent. the driver out square wave starts with a duty cy cle of 50%. after tree or four cycles the duty cycle can reach its maximum. as far as the peak current will stay smaller than ia peak this duty cycle maximum is really 100%. if during the ramp up of the antenna current the envelope of the peak current will be greater than ia peak + 20% a pulse skipping function will suppress the next driver output pulse to minimize the antenna current overshoot. 4.7 diagnosis and protection the ic supervises several parameters of ic operation for transmission diagnosis and circuit protection. in any case of circuit protection mode or error detection the ic indicates this states according to the transmission protocol via the dio line (see section ?transmission acknowledge and error signal? on page 6 ). ia peak 750 ma 50 k ? r cr --------------- =
9 4909b?auto?04/06 ata5276 [preliminary] 4.7.1 circuit protection cases the circuit protection is activated in normal mode, i. e., if the antenna circuit is driven to the oscil- lation with its own frequency. it is switched off in standby mode. between the end of the transmission and the acknowledge signal the low side driver is switched on. in case a protection switch-off occurs the half-bridge is set in tri-state mode. for all cases, there is a filter implemented to debounce half-bridge switch-off for a time of t deb (typically 20 s). this debounce filter is activated in case the half-bridge is activated. these are the following circuit protection cases: 1. load dump protection: in case the voltage at dvcc exceeds a voltage vbat ld (typi- cally 31v). 2. overtemperature protection: in case the junction temperature exceeds a value of tsd (typically 165c). 4.7.2 error diagnosis during the transmission the diagnosis function of the ic supervises the antenna current and fre- quency and the half-driver bridge supply voltage. if any error is detected at the end of the transmission cycle the error indication is set (as in circuit protection case). there are the following diagnosis cases: 1. under-voltage detection: monitors if dvcc is below vbat uv (typically 6.5v). 2. antenna frequency erro r: diagnosis if the oscillation frequency during tr ansmission is outside the typical tracking range 90 khz to 160 khz. 3. antenna peak current error: diagnosis if the peak current is greater than the adjusted ia peak + 15% typically.
10 4909b?auto?04/06 ata5276 [preliminary] electrostatic sensitive device. observe precautions for handling. 5. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. max. unit ground vss 0 0 v power ground dvss1,2,3 ?0.3 +0.3 v reverse protected battery voltage dvcc1,2,3 ?0.3 +44 v half-bridge driver output drv1,2,3 ?0.3 dvcc + 0.3 v bootstrap boost ?0.3 dvcc + 6 (2) v 5-v regulator output vcc ?0.3 +7 v analog reference input rext ?0.3 vcc + 0.3 v rcr ?0.3 vcc + 0.3 v digital test mode tm1,2,3 ?0.3 vcc + 0.3 v dio interface supply vdio ?0.3 dvcc + 0.3 v dio interface dio ?0.3 dvcc + 0.3 v zero crossing analog input sense ?2 dvcc + 0.3 v electromagnetic interference emi 250 v/m minimum esd protection (100 pf through 1.5 k ? ) at pins 3, 4, 5 and 19 1.5 (on pcb) kv minimum esd protection (100 pf through 1.5 k ? ), all other pins 2 (on pcb) kv power dissipation p tot 2 (1) w junction temperature ? j 150 c storage temperature ? store ?55 +125 c ambient temperature range under bias ? ambient ?40 +105 c soldering temperature (10s) ? soldering 260 +0/?5 c notes: 1. may be limited by external thermal resistance. 2. if the low side driver is switched on, it is not allowed to connect a voltage source to pin boost. 6. thermal resistance parameters symbol value unit thermal resistance, junction ambient r thja 35 k/w 7. operating range the operating conditions define the limits for functional operat ion and parametric characteristics of the device. functionality outside these limits is not implied if not otherwise stated explicitly. parameters symbol value unit operating supply voltage v vbat1 8 to 24 v operating temperature range ? amb ?40 to +105 c
11 4909b?auto?04/06 ata5276 [preliminary] 8. noise and surge immunity parameter test conditions value conducted interferences iso 7637-1 level 4 (1) note: 1. test pulse 5: v smax = 45v 9. electrical characteristics (1) no. parameters test conditions pin symbol min. typ. max. unit type* 1power supply 1.1 main supply voltage i(vcc) = 10 ma, including load and line regulation vcc v cc 4.7 5.0 5.3 v a 1.2 supply current without antenna load dvcc i supp 21020maa 1.3 standby current pin dvcc = 13.5v, t amb = 90c dvcc i stby 20 35 60 a b 1.4 power-on-reset threshold voltage vcc v por 3.544.5va 1.5 load dump protection voltage dvcc vbat ld 29 31 35 v a 1.6 under voltage detection dvcc vbat uv 6.0 6.5 7.0 v a 1.7 thermal shut down tsd 150 165 180 o cb 1.8 protection debounce filter t deb 10 15 25 s a 2 half-bridge driver stage 2.1 coil driver resistance low side driver drv, dvss rds onl 0.3 0.7 ? a 2.2 coil driver resistance high side driver dvcc, drv rds onh 0.3 0.7 ? a 2.3 driver output rise time 10% to 90% slope time, 0% = dvss, 100% = dvcc dvcc = 12v (smooth edges) drv t drv,rise 50 100 150 ns d 2.4 driver output fall time 10% to 90% slope time, 0% = dvss, 100% = dvcc dvcc = 12v (smooth edges) drv t drv,fall 50 100 150 ns d *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. 8v < v(dvcc) < 24v; ?40 c < ? amb < 105 c, unless otherwise specified; all values refer to gnd 2. definition of dc drv see ?application hints? on page 14 3. i vdio,stby = 7.5 a at t amb = 90c
12 4909b?auto?04/06 ata5276 [preliminary] 3 antenna peak current control 3.1 duty cycle control range drv dc drv (2) 15 85 % b 3.2 peak current control reference rcr v rcr 1.15 1.215 1.28 v a 3.3 peak current control accuracy r cr = 25 k ? ia peak 1.0 1.5 1.8 a b 3.4 antenna peak under current threshold 0% nom value = ia acc rcr = 25 k ? ia uc ?30 ?20 ?10 % a 3.5 antenna peak overcurrent threshold 0% nom value = ia acc rcr = 25 k ? ia ov 30 20 10 % a 4 oscillator and phase control 4.1 vco initial frequency self oscillating mode = half-bridge not activated clk so 115 125 135 khz a 4.2 vco frequency tracking range tracking frequency mode = half-bridge activated clk tr 80 200 khz b 4.3 phase shift between voltage at drv and zero crossing of current through sense antenna resonance frequency range = 100 khz to150 khz, antenna quality = 5 to 50 drv, sense ? a ?120 0 +120 ns b 4.4 phase control set-up time ?240 ns ? a +240 ns drv, sense t setup 160 s d 4.5 high frequency failure threshold drv f vcoh 150 160 200 khz a 4.6 low frequency failure threshold drv f vcol 80 90 105 khz a 5 dio interface 5.1 vdio leakage current pin vdio = 13.5v, pin dio = 13.5v t amb 27c (3) vdio i vdio,stby 245aa 5.2 dio leakage current pin vdio = 13.5v, pin dio = 13.5v t amb = 90c dio i dio,leak 5.5 10 15 a a 5.3 dio sink current dio i dio,limit 36 44 52 ma a 5.4 output low level i dio = 20 ma dio v diol 1.2 1.5 v a 5.5 input low level threshold 100% = dvcc dio v dio,thl 30 45 70 %v (vdio) a 5.6 input high level threshold 100% = dvcc dio v dio,tlh 30 50 70 %v (vdio) a 9. electrical characteristics (1) (continued) no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. 8v < v(dvcc) < 24v; ?40 c < ? amb < 105 c, unless otherwise specified; all values refer to gnd 2. definition of dc drv see ?application hints? on page 14 3. i vdio,stby = 7.5 a at t amb = 90c
13 4909b?auto?04/06 ata5276 [preliminary] 6 transmission protocol 6.1 lf data baud rate bd rf 1 4 kbit/s c, d 6.2 anti-bouncing time for activate half-bridge dio = h l, for f vco = 125 khz t dl 64 s b 6.3 anti-bouncing time for de-activate half-bridge dio = l h, for f vco = 125 khz t dh 64 s b 6.4 acknowledge pulse width t ack 256 s b 6.5 error signal pulse width t err 128 s b 6.6 transmission time out de-activated half-bridge t outl 16 ms b 6.7 transmission time out activated half-bridge t outh 16 ms 6.8 time out reset pulse width t or 32 s 6.9 time out reset pulse period t orp 15 ms 9. electrical characteristics (1) (continued) no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. 8v < v(dvcc) < 24v; ?40 c < ? amb < 105 c, unless otherwise specified; all values refer to gnd 2. definition of dc drv see ?application hints? on page 14 3. i vdio,stby = 7.5 a at t amb = 90c 10. external components the following external components have to be applied to the circuit for functional operation (see figure 11-1 on page 15 ). component pin min. typ. max. unit c1 dvcc 100/50 f/v d1 standard diode 1.5/50 a/v r ext rext 100 k ? r cr rcr (3) 25 200 k ? c3 vcc 10 f c2 boost 0.68 1 2 nf r sense sense (1) 0.1 (2) 0.5 1 ? r dio dio 0.6 1 6 k ? l ant antenna inductance 345/2.5 h/ ? r ant q-factor adjuster 10 ? c ant resonant-frequency adjuster 4.7/400 nf/v notes: 1. sensitivity at input sense is proportional to resistor rs times antenna peak current. 2. for antenna peak value 1.5a. 3. recommended range: r cr = 25 to 100 k ? .
14 4909b?auto?04/06 ata5276 [preliminary] 11. application hints a typical application of ata5276 is shown in figure 11-1 on page 15 . the peak value of the antenna current can be estimated by the formula: here r a denotes the equivalent series resistance of the driver load, i.e., the external coil series resistance in series with the shunt resistance and the internal drain-source-on-resistance of the ndmos. the duty cycle dc drv is the ratio of the driver high-side on-time with respect to the half of the oscillation period. the phase difference ? a is measured as the time differenc e between the point of mass of vdrv and the peak value of the antenna current. ? a 2 -- - v dvcc r a ----------------- sin 2 -- - dc drv ?? ?? cos ? a =
15 4909b?auto?04/06 ata5276 [preliminary] figure 11-1. application circuit vbatt 8 to 24v gnd l ant d1 r s c ant r ext c1 microcontroller or ecu lf receiver r cr r shunt c2 drv c3 ata5276 125 khz transmitter duty cycle regu - lator vco 5v reg. k- line refe- rences gate driver control state machine off sense current clk bus ref- ext on/ drv 19 boost 14 tm2 15 tm1 13 tm3 9 sense 6 dvss3 8 dvss1 7 dvss2 3 drv3 4 drv2 2 dvcc1 1 dvcc2 10 vss 5 drv1 half bridge 12 rcr 11 rext 17 dio 16 vdio 18 vcc 20 dvcc3 r dio c dio note: for the typical values of the external components, see table "external components" on page 13.
16 4909b?auto?04/06 ata5276 [preliminary] 13. package information 12. ordering information extended type number package remarks minimum order quantitiy ATA5276-PGQW qfn20, 5 mm 5 mm pb-free, taped and reeled 6,000 ata5276-pgpw qfn20, 5 mm 5 mm pb-free, taped and reeled 1,500
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